1. Technical Field
The present invention relates to a semiconductor device having a cylindrical dummy wire to surround the outer circumference of a semiconductor element.
2. Description of the Related Art
In recent years, degree of integration at the level of an element such as a transistor has been rapidly improved with the development in miniaturization of a semiconductor device such as a microprocessor and a memory. For this reason, there has been a necessity of a multi-layer wire to achieve high integration of a wire system in accordance with high integration at the level of a substrate. However, signal delay, i.e., RC delay, in the wire layer is increased due to the extension of a conventional process accompanying the miniaturization of the wire system, which hinders the increase of operation speed. Therefore, it is absolutely necessary to reduce wire resistance R and inter-wire capacity C in order to achieve further increase in speed of the microprocessor or the like. For the reduction of the wire resistance R, it is possible to greatly reduce a resistance value by changing a material for the wire from aluminum to copper. It is extremely difficult to etch copper, unlike aluminum, whereas the copper is relatively easily formed with a thickness film by a chemical vapor deposition (CVD) method as a method of forming a thin film having excellent step coverage or a plating method for filling-in. A damascene method as a process taking such merits of copper while excluding demerits of the copper is known. The damascene method is a technology for pre-forming a groove for a wire in an interlayer insulation film, depositing a copper film on the entirety of a wafer such that the groove is filled with the copper film, removing the remaining copper film excluding the portion of the copper film filling the groove using a chemical mechanical polishing (CMP) method, and forming a copper wire in the interlayer insulation film.
For the reduction of the inter-wire capacity C, on the other hand, the introduction of a so-called low-k film having a lower relative dielectric constant instead of a conventional SiO2 film as a material of the interlayer insulation film is under consideration. Since poly silsesquioxane containing methyl (MSQ) attracting attention as a material of the low-k film generates a gap in a molecular structure by the presence of a methyl group, such a film is porous. This low-k film having a low film density is highly hygroscopic. In addition, the dielectric constant of the low-k film is increased due to introduction of impurities, and therefore, the reliability of the low-k film is low. Furthermore, the low-k film is easily broken due to low mechanical strength of the low-k film when stress is applied by dicing and bonding. Also, interlayer separation may occur due to low interface adhesion of the low-k film. When such breakage or interlayer separation occurs, the low-k film absorbs external moisture because the hygroscopic property of the low-k film is high, with the result that the moisture is transmitted to an active region, which is a chip region, whereby the semiconductor device becomes defective, and its yield ratio is lowered.
To solve the above-described problem at the time of dicing, Patent document 1 discloses a structure in which a so-called seal ring is provided such that a bonding pad forming region and an active region are surrounded by a metal wire. Also, to solve the above-described problem at the time of bonding, Patent document 2 discloses a structure in which a so-called seal ring is provided such that the outer circumference of a bonding pad forming region is surrounded by a metal wire.    Patent document 1: Japanese Patent Kokai No. 2005-167198    Patent document 2: Japanese Patent Kokai No. 2005-142553